Adaptive Hybrid Storage Format for Sparse Matrix–Vector Multiplication on Multi-Core SIMD CPUs

Optimizing sparse matrix–vector multiplication (SpMV) is challenging due to the non-uniform distribution of non-zero elements matrix. The best-performing SpMV format changes depending on input matrix and underlying architecture, there no “one-size-fit-for-all” format. A hybrid scheme combining multiple storage formats allows one choose an appropriate use for target hardware. However, existing approaches are inadequate utilizing SIMD cores modern multi-core CPUs with SIMDs, it remains unclear how best mix different a given This paper presents new matrices, specifically targeting SIMDs. Our approach partitions into two segmentations based regularities memory access pattern, where each segmentation stored in suitable its patterns. Unlike prior schemes that rely user determine data partition among formats, we employ machine learning build predictive model automatically threshold per basis. first trained off line, can be applied any new, unseen We apply our 956 matrices evaluate performance three distinct CPU platforms: 72-core Intel Knights Landing (KNL) CPU, 128-core AMD EPYC 64-core Phytium ARMv8 CPU. Experimental results show scheme, combined model, outperforms alternative by 2.9%, 17.5% 16% average KNL, AMD, Phytium, respectively.